The susceptibility of dynamic random access (DRAM) and static random access (SRAM) devices to alpha particle degradation has long been recognized. The problem was discovered early in the evolution of semiconductor memory devices but has become severe since the advent of very high density MOS transistor memory arrays. These arrays store data in the form of electrons or holes (usually electrons in n-channel devices) and a very few charges represent a data bit in a very high density array. Thus a single alpha particle "hit" in a storage capacitor of one of these devices will generate enough hole-electron pairs that the charge state of a capacitor in e.g. the "zero" state (no charge) will be read as a "one".
A variety of approaches have been used for protecting these devices from alpha particle exposure, typically from alpha particle sites outside the device package. Thus packaging designs are known which shield the package contents, i.e. the memory arrays, from alpha particle exposure. It has also been recognized that certain types of device packages, e.g. certain metal containers, can be sources of alpha particle contamination and either are to be avoided, or steps taken to insulate the chip from the alpha particle source. Generally, the art of memory chip packaging is well developed and the conventional memory chip packages are largely free of alpha particle problems.
Standard memory chip packages, which now have essentially proven alpha particle immunity, are dual in-line packages, and more recently, surface mount quad packages. Both of these device packages often use solder connection between the leads or pads on the encapsulated IC, and printed wiring boards or other interconnect substrates. Typically the solder is standard lead-tin solder.
The conventional memory packages, i.e. die- and wire-bonded leaded packages, impose a cost in terms of performance and size that is now being seen as too high for certain applications, and more sophisticated memory chip packaging approaches are sought. For many years the trend in semiconductor device and package design was in ever higher levels of integration, which in memory technology took the form of integrating memory and logic on the same chip. Power modules and driver circuits are conventionally part of DRAM and SRAM devices, and many memory device designs have application specific logic embedded with the memory arrays on a common chip. However, while logic and memory semiconductor elements share many common features, there are differences. For example, a critical feature of a memory element is the storage capacitor. This element must be made optimally small, and essentially without defects or leakage. Logic devices have no comparable element, and are more forgiving in some device aspects. Consequently a wafer fabrication process that is tailored for memory device optimization is not usually optimum for logic devices. Thus, compromises are made in order to have different device species on the same semiconductor chip.
Current developments are proceeding in the direction of "disintegration", where memory devices consist mainly of memory cells, and the "on-board" logic and other transistors are put on another chip. These chips can be processed optimally for the size and nature of their components. In this technology, the "integration" is performed at the package level, and the key to its success is a packaging technology that produces a final product that is superior to a chip integrated system in performance and cost, and at least comparable in size.
A leading candidate for this packaging technology is flip chip bonding and assembly. Flip chip bonding is a well developed technology and is characterized by bonding bare silicon IC die upside down on an interconnect substrate such as a printed wiring board. Several bonding techniques have been developed, e.g. ball bonding, ball grid array (BGA--a form of ball bonding), and solder bump bonding. These techniques lead to reduced I/O pitch through smaller contact surfaces, and area rather than perimeter interconnection arrays. Moreover, electrical performance is enhanced because lead lengths are reduced. Typically, the bonding method in these techniques is solder bonding.
We have recognized that the miniaturization of interconnections in these advanced technologies introduces new and unexpected consequences. Essentially unknown to the developers of wire bonds, and extended leads typical of through mounted and surface mounted packages, is that the leads in these techniques are inherently long enough to provide beneficial isolation of the active circuit elements, i.e. transistors, from alpha particle sources in the solder interconnections. As those leads are shortened, as they are in the improved technologies described above, the active elements of the ICs are brought closer to the solder interconnections. We have recognized that a consequence of very close proximity of a solder interconnection to a susceptible IC component is that alpha particles emitted from the solder can impact the semiconductor substrate in the vicinity of the active element and cause alpha particle damage as described earlier. The alpha particle problem is most severe when the interconnection comprises a lead based solder.
One approach to overcoming the alpha particle problem is to locate the I/O leads far enough away from the susceptible circuit elements to spatially isolate the latter from alpha particles emitted from the solder. To some extent this is achievable in large packages with perimeter I/O pads. However, in the new packaging technologies of interest to state of the art designers, the best interconnection approaches use area arrays of I/O pads, where I/O pads are located directly adjacent potentially susceptible circuit elements. Moreover, even perimeter I/O pads are situated very close to active elements in the very small packages currently being designed.